All hardware design files are free - licensed under CERN Open Hardware Licence (CERN OHL).
Hardware is built around Xilinx Artix-7 FPGA with an onboard RAM available for buffering samples (512 MB DDR3 SDRAM). All hardware settings are controlled via software GUI. USB connectivity is provided via Cypress’s FX3 USB 3.1 Gen1 chip. Hardware is USB powered which eliminates the need for additional power supply. Below you can find more information about individual hardware components.
Two analog channels are available as oscilloscope inputs. Both oscilloscope channels are protected against overvoltages up to +/- 50 V. Input coupling selection is available (DC, AC, GND) and is controlled via program GUI. Input signals are buffered via analog front end for impedance, level (gain) and offset adjustments. Each analog channel is sampled at 250 Msps with 10-bit analog-to-digital converter (ADC). Two ADC's can be configured for sampling in interleaved mode which provides a single channel sampling speed of 500 Msps. Digital samples are processed by FPGA which also contains trigger logic. When trigger condition is met, samples are transferred to onboard DDR3 SDRAM which provides buffer length of 128 Mega samples per channel. Hardware also supports Equivalent Time Sampling (ETS). For this purpose an analog trigger signal is sampled inside FPGA LUT delay line to determine exact time of trigger event relative to the ADC sampling clock. This provides a sampling speed of 2 GSps for repetitive signals.
There are two generator outputs with which can generate voltages up to 4 Vpp. Both AWG channels are protected against short circuit and overvoltage (+/- 25 V). Generator channels have 50 Ohm output impedance which allows connection to various equipment. User can select waveform shape, frequency, level and offset via program GUI and settings are immediately reflected in FPGA control registers. Digital samples are generated inside FPGA at 200 Msps per channel and transferred to dual digital-to-analog converter (DAC). Simple signals are derived from counters. Sine wave output is generated with the help of CORDIC algorithm, so that outputs of arbitrary frequency can be obtained. User can also provide a custom waveform sample data and upload it to FPGA internal memory (BRAM).
12-bit digital interface is sampled at 250 Mhz and is logically divided into two 6-bit channel groups. Each channel group can be independently selected as input (Logic analyzer) or output (Pattern generator). Digital interface voltage can be adjusted - ranging from 1,25 V to 3,3 V, but inputs are designed to accept also 5 V. Selected interface voltage is also available on dedicated output pins and can be used as voltage supply. Custom digital samples for pattern generator can be uploaded to FPGA and internal clock divider is available to control the output frequency. It is also possible to override individual outputs with a logic 'LOW' or 'HIGH' at any time.
Logic Analyzer / Pattern Generator