Analog Trigger

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Analog Trigger
« on: November 04, 2017, 09:46:33 AM »
In the documentation on web, following Analog Trigger properties are given. However, if I go to schematics, I am only able to find Analog Trigger Level is coming from FPGA and is being fed to comparator at Channel A. But I do not see anything for Channel B or external Digital Trigger.

Source: Analog Ch. 1, Analog Ch. 2, Digital Ch. ( external ), Generator Ch. 1, Generator Ch. 2
Mode: Auto, Normal, Single ( with Re-Arm )
Pre-Trigger: Adjustable 0 - 100 %
Trigger Level: 0 - 100 %
Trigger Level Hysteresis: Adjustable
Trigger Holdoff: Adjustable 0 - 4,2 s ( 10 ns step size )
Digital trigger: 4 stages ( with delay counter for each stage )
Digital trigger: selective channel masking ( logic levels: '0', '1', 'Rising', 'Falling' )

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Dejan

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Re: Analog Trigger
« Reply #1 on: November 05, 2017, 04:21:56 PM »
I will try to explain the trigger design...

There are two modes of operation: Real-time sampling and equivalent-time sampling. The trigger is implemented differently in each mode.

In the real-time sampling mode, the trigger events are detected by FPGA internal logic. FPGA is continuously sampling all the inputs and when the trigger conditions are met, samples are saved to buffer. External comparators are not needed, because all the trigger logic is inside FPGA. All inputs (analog & digital) and outputs (AWG & digital) can be used as trigger source in this mode.

In ETS mode it is possible to reconstruct the signal if we know the exact time of trigger event relative to sampling clock. For this purpose the analog input signal is sent to comparator which generates the trigger pulse. This pulse is then fed to a tapped delay line inside FPGA and the outputs of delay line are sampled to determine exact time of trigger event. In this mode only channel 1 can be used as trigger source.

Re: Analog Trigger
« Reply #2 on: November 05, 2017, 10:56:27 PM »
Understood. Thanks for explaining.

Re: Analog Trigger
« Reply #3 on: January 28, 2020, 12:09:05 AM »
I wonder if you could use the LUT-delay trigger measurement to make successive traces appear less jittery even in real time mode?  Just offset where you plot the trace on the screen depending on this measured delay..

BTW, I found a paper that mentions using the carry chain for even finer accuracy:

https://arxiv.org/pdf/1303.6840.pdf

« Last Edit: January 28, 2020, 05:50:24 PM by jhallen »

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Dejan

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Re: Analog Trigger
« Reply #4 on: February 21, 2020, 10:28:20 AM »
@jhallen, thank you for the idea. You got me thinking some time about this... :-)

The trace jitter will be one clock period (4 ns @ 250 Msps) which is noticeable only when looking at high speed signals. Usually when you observe a high speed repetitive signal, you can enable ETS mode and the time of trigger will be determined accurately using the LUT delay line. You could still use the the same input for the trigger event indicator in real-time mode, but there are some limitations because the ETS trigger input comes from analog comparator. The analog comparator has no trigger hysteresis or slope setting, only trigger level can be adjusted. The other question is, would it be really useful for observing signals in real time mode? Usually in real time mode you are looking at non-repetitive signals where each frame is plotted differently, so the trace jitter will not be obvious.

Regarding delay measurement using the carry chains, we have considered this but normally the user doesn't need such high accuracy. With LUT lines we can have about 0.5 ns resolution (2 GSPS) which is enough considering that the input bandwidth of the analog inputs is 100 Mhz. Also the implementation with carry chains requires more resources in the FPGA and is more complex.