Adc fpga synchronisation

Hi everyone!
This project looks really interesting. I'm trying to understand how you sync the ADC clock with the fpga clock.

Q1.
I assume the artix 7 fpga runs at 500mhz clock rate and that the ADC feeds bits (10 bit signal) through 10 parallel wires at the same 500mhz clock rate.

Is this correct?

Q2.
Do the fpga and adc share the same clock? Or just two separate clocks running at the same speed?

Thanks guys, excited to see all developments

John

Hello and welcome to the forum

Artix 7 fpga runs at 250 MHz. The FPGA clock comes from the ADC through the DDR-LVDS interface (see attached image).

The clock source for the ADC comes from oscillator.