That depends on other requirements, but in any case, additional memory is needed to store AWG samples. The existing FPGA BRAM is currently 80% utilised, so only a slight increase is possible with the current architecture. But this would be the simplest way as only the FPGA BRAM address counter would have to be expanded. It could also be possible to assign all existing FPGA BRAM only to single AWG, that would give about 3x more memory, so about 100k custom samples. Some additional changes would have to be done on the FPGA side and also software side.
If you do not require the two oscilloscope channels, CH1 and CH2, it would be possible to use all of the onboard 512 MB of SDRAM for this purpose. If you were also to keep oscilloscope channels, this would also require a synchronisation of SDRAM access (to save ADC samples and read AWG samples simultaneously). Unfortunately, I would't say that would be a simple process.