Open source

All hardware design files are free - licensed under CERN Open Hardware Licence ( CERN OHL ).

Design overview

Hardware is built around Xilinx® Spartan®-6 LX9 FPGA which contains digital logic. All hardware settings are controlled via program GUI and transferred to FPGA registers via Cypress’s EZ-USB® FX2LP™ chip. Below you can find more information about individual hardware components.

Oscilloscope

Two analog channels are available as oscilloscope inputs. Both oscilloscope channels are protected for overvoltage up to +/- 50 V. Input coupling selection is available ( DC, AC, GND ) and is controlled via program GUI. Input signals are buffered via analog front end for impedance, level ( gain ) and offset adjustments. Analog signals are sampled at 100 Mhz through an 10-bit dual analog-to-digital converter ( ADC ). Digital samples are then processed by FPGA which contains trigger logic. When trigger condition is met, samples are first buffered in FPGA internal RAM ( BRAM ) and then transferred to PC via FX2LP USB chip.

Waveform Generator

There are two generator outputs with short circuit and overvoltage protection ( +/- 50 V ). Generator channels have 50 Ohm internal impedance which allows connection to various equipment. User can select frequency, output level and offset via program GUI. Generator  settings are transferred to FPGA registers via FX2LP USB chip. Digital samples are generated in FPGA at 50 Mhz and sent to digital-to-analog converter ( DAC ). Simple signals are derived from counters. Sine wave output is generated with the help of CORDIC algorithm, so that outputs of arbitrary frequency can be obtained. User can also select a file containing custom waveform samples which is uploaded to FPGA internal memory.

Logic Analyzer / Pattern Generator

16-bit digital interface is sampled at 100 Mhz and is logically divided into two 8-bit channel groups. Each channel group can be independently selected as input ( Logic analyzer ) or output ( Pattern generator ). Digital interface voltage can be adjusted - ranging from 1,25 V to 3,3 V, but inputs are designed to accept also 5 V. Selected interface voltage is also available on dedicated output pins and can be used for voltage supply. Custom digital samples for pattern generator can be uploaded via GUI and internal clock divider is available to control the output frequency. It is also possible to override individual outputs with a logic 'LOW' or 'HIGH' at any time.

 


Specifications

Oscilloscope

  • No. of Channels: 2
  • Sampling rate, max.: 100 Msps Real-Time / 3.2 Gsps with Equivalent-Time Sampling ( ETS )
  • Sampling rate, min.: 1 sps
  • Resolution: 10 bit
  • Memory depth: 10.000 Samples per channel
  • Voltage range: 10 mV/div - 2 V/div ( with 1× probe ); 100 mV/div - 20 V/div ( with 10× probe )
  • Input Offset: adjustable ( +/- 100 % )
  • Input coupling: DC, AC, GND
  • Input impedance: 1 MΩ || 12 pF
  • Overvoltage protection: +/- 50 V ( permanent )
  • LED trigger indicator

Waveform Generator

  • No. of Channels: 2
  • Sampling rate: 50 Msps
  • Resolution: 12 bit
  • Output impedance: 50 Ω
  • Waveform shapes: Sin, Cos, Triangle, Saw, Ramp up/down, Delta, DC, Noise, Custom
  • Custom waveform memory depth: 4.096 Samples per Channel
  • Max out. Voltage: +/- 2,0 V
  • Offset and Level adjustable
  • Overvoltage protection: +/- 50 V ( permanent )
  • Short-circuit protection

Logic Analyzer / Pattern Generator

  • No. of Channels: 16 ( logic analyzer / pattern generator: 8-input / 8-output; 16-input; 16-output )
  • Sampling rate: max. 100 Msps
  • Interface voltage: Adjustable 1,25 V - 3,3 V in 256 steps
  • Memory depth: 10.000 Samples per channel
  • Input Impedace ( Logic Analyzer ): 200 kΩ
  • Output Impedance ( Pattern Generator ): 1 kΩ
  • Overvoltage protection: +/-5 V ( Permanent ); +/- 20V ( Short term ~ 15 s )
  • Pattern Generator memory depth: 4.096 Samples per Channel
  • Pattern Generator internal clock divider: Adjustable 32-bit ( 100 Mhz - 0,023 Hz )

Trigger

  • Source: Analog Ch. 1, Analog Ch. 2, Digital Ch. ( external ), Generator Ch. 1, Generator Ch. 2
  • Mode: Auto, Normal, Single ( with Re-Arm )
  • Pre-Trigger: Adjustable 0 - 100 %
  • Trigger Level: 0 - 100 %
  • Trigger Level Hysteresis: Adjustable
  • Trigger Holdoff: Adjustable 0 - 4,2 s ( 10 ns step size )
  • Digital trigger: 4 stages ( with delay counter for each stage )
  • Digital trigger: selective channel masking ( logic levels: '0', '1', 'Rising', 'Falling' )